The present invention relates to a method for transmitting an address to a memory for the purpose of reading or writing data, the memory comprising memory cells for storing data, an address bus and a data bus. The invention also relates to a memory which comprises memory cells for storing data, an address bus and a data bus, as well as to a memory interface for the memory which memory comprises memory cells for storing data as well as an address bus and a data bus. Furthermore, the invention relates to a communication device comprising a memory which contains memory cells for storing data and an address bus and a data bus for addressing the memory cells.
In synchronous DRAM memories (SDRAM) of prior art, the memory cells are organized in a matrix form, wherein the SDRAM memory is provided with a control logic, by means of which it is possible to address each memory cell of the matrix. The control logic comprises means for addressing a matrix row and means for addressing a matrix column. Writing and reading information from such SDRAM memories is conducted in blocks in such a way that at first, the initial address and the length of the block is transmitted to the SDRAM memory, after which the data is read or written synchronously under the control of a clock signal. The address is transmitted in two phases typically in such a way that in the first phase, the row address of the matrix corresponding to the target address, and in the second phase the column address of the matrix is written in the SDRAM memory. From these row and column addresses, the control logic of the SDRAM memory generates a signal to address the correct memory cell in the matrix. These row and column addresses are written along the same address lines, with the difference that when writing the row address, the SDRAM memory is notified by a separate row address strobe line that it is the row address in question, and correspondingly, when writing the column address in the SDRAM memory, a separate colum address strobe line indicates that the address in question is the column address. The appended FIG. 1 presents a timing plan indicating such an SDRAM memory of prior art when writing or reading data.
The synchronous DRAM memory differs from a conventional DRAM memory primarily in that from the synchronous DRAM memory, data is read and written in bursts. At the initiation stage, the synchronous DRAM memory is notified, by means of the above-presented address mechanisms, of the length of the burst to be read or written. First, when the data is to be read or written, the synchronous DRAM memory is notified of the initial address of the block to be read or written, after which an address counter is increased in the memory in order to address the next memory cell after reading or writing the preceding information. The length of the burst is preferably notified only once if the length of the burst changes. However, when using the conventional DRAM memory, each byte to be read or written should be externally provided with a separate memory address, i.e. with a separate row and column address for each memory cell to be read. In this way the speed of the synchronous DRAM memory is increased when compared with the conventional DRAM memory. This is useful especially if the data to be read or written is sequential by nature. However, in situations when data is read randomly from various locations, for example one byte at a time, the speed of the synchronous DRAM memory does not necessarily exceed the speed of the conventional DRAM memory.
The synchronous DRAM memory can be advantageously used as a data memory for a processor, as a display memory in video applications, and as a storage location for a program code of an application, especially in situations when an increase is desired in the execution rate. Read only memories (ROM) are typically slower than sychronic DRAM memories, wherein the program code of the application or part of it is loaded from the read only memory into the SDRAM memory before executing the application. In systems which use two or more processors, the same synchronous DRAM memory can be utilized for storing the program codes of these different processors during the execution. Since the same SDRAM memory is used for several functions, the speed of this SDRAM memory easily becomes a significant factor affecting the performance of the system. The speed of the processors and possible cache memories can be increased by increasing the clock frequency with new manufacturing processes, but the data rate of the external memory interface cannot be significantly increased in this manner. Thus, in some situations, the load on the memory bus can exceed 100%, wherein the performance of the entire system is affected by the slowness of the memory bus.
Processors use the SDRAM memory in electronic devices typically via cache memories. The cache memory of a processor is divided into blocks of fixed size. Thus, one block is read from the SDRAM memory into the cache memory or written from the cache memory into the SDRAM memory at a time. The processor has to, for example, retrieve information from the SDRAM memory. At first, the processor examines, whether the information is loaded in the cache memory e.g. due to a preceding reading operation. If the information is in the cache memory, it is available for the processor. In other cases, the data is retrieved from the SDRAM memory. The processor sets the initial address in which the data to be read is located in the SDRAM memory as well as the length of the block to be read, for example 16 bytes. After this, the block is read from the SDRAM memory into the cache memory, from which the processor can retrieve the read information. Writing takes place reversely with a corresponding principle. Also, when using the SDRAM memory as a display memory, data is typically read in blocks into the display driver. Data transmission can be implemented either via a processor or via a separate memory manager (DMA, Direct Memory Access Controller). In case the desired information is not found in the cache memory, the information has to be retrieved from the SDRAM memory into the cache memory. Thus, the processor has to wait during the entire transfer, wherein the performance of the processor falls practically into zero. Thus, the time consumed by the reading/writing operation between the cache memory and the SDRAM memory affects the performance of the processor.
A known solution for the aforementioned performance problem is to increase the width of the data bus for example from 16 bits to 32 bits, or to increase the clock frequency of the external memory bus. However, increasing the bus width requires a larger number of connecting pins outside the memory circuit, which increases the physical size of the circuit and the size of the semiconductor material used in the manufacture of the circuit, as well as the power consumption of the circuit. Increasing the clock frequency, in turn, increases the power consumption of the memory circuit correspondingly; for example by increasing the clock frequency by 30%, the power consumption in the memory circuit is increased by 30%.
One purpose of the present invention is to provide a faster data transmission method to and from a memory, a bus interface, and a memory. The invention is based on the idea that a data bus is also used as an address bus. The method according to the present invention is characterized in what will be presented in the characterizing part of the appended claim 1. The dynamic memory according to the present invention is characterized in what will be presented in the characterizing part of the appended claim 6. The memory interface according to the present invention is characterized in what will be presented in the characterizing part of the appended claim 10. Furthermore, the communication device according to the present invention is characterized in what will be presented in the characterizing part of the appended claim 5.
With the present invention, considerable advantages are achieved when compared with solutions of prior art. With the method according to the invention, the data reading and writing rate can be significantly increased when compared with solutions of prior art. Since the memory addressing according to the invention uses a data bus also as an address bus, separate sequences for addressing the rows and columns are not necessary, and neither are separate strobe lines for row and column addresses. Thus, the row and column addresses can be transferred substantially simultaneously into the memory circuit. Furthermore, a smaller number of interface lines is required when compared with solutions of prior art. The performance is enhanced without increasing power consumption, which is a significant advantage especially in portable electronic devices.